Integrated circuit devices, such as integrated circuit memory devices and integrated circuit logic devices, are widely used in consumer and commercial applications. Recently, Merged Memory and Logic (MML) integrated circuit devices have been developed. MML integrated circuit devices generally include a large capacity memory and a large logic block that are merged in one integrated circuit device. Thus, an MML integrated circuit device can replace discrete memory and logic chips that are used in personal computers and other consumer and commercial devices. MML devices are described, for example, in U.S. Pat. No. 5,848,016 to Kwak, entitled "Merged Memory and Logic (MML) Integrated Circuits and Methods Including Serial Data Path Comparing", and assigned to the assignee of the present application, the disclosure of which is hereby incorporated herein by reference.
MML integrated circuit devices may present new challenges for the testing thereof. In particular, an MML integrated circuit device generally provides a large number of internal data paths between the memory block and the logic block. For example, up to 256 or more internal data paths may be provided. Since many of these internal data paths are not brought out to external MML integrated circuit device pads, it may be difficult to access all of the internal data paths in order to test the memory block.
Stated differently, in order to test a conventional memory integrated circuit device, test equipment is coupled to the pads of the memory integrated circuit device. However, the memory block in an MML integrated circuit device may be difficult to test because the memory is connected to the external pads through the logic block.
It is also known to provide MML integrated circuit devices that include a buffer memory, generally having a smaller capacity than the memory block. The buffer memory is connected to the memory block and generally operates at a higher speed than the memory block. For example, the memory block may be a Dynamic Random Access Memory (DRAM) and more preferably a synchronous DRAM, and the buffer memory may be a Static Random Access Memory (SRAM). The buffer memory operates as a buffer between the memory block and the logic block. Thus, the memory block transmits and receives data only to and from the buffer memory. The logic block also transmits data to and receives data from the buffer memory.
In an MML integrated circuit device that includes a buffer memory between a memory block and a logic block, it may be difficult to test the memory block. In particular, in a conventional integrated circuit memory device, the memory cells of the memory device may be tested by directly accessing the memory from external of the integrated circuit memory device. It is known to use a multiplexer to select different modes, such as a normal operation mode, an external test mode and a Built-In Self-Test (BIST) mode, to directly access the memory.
In an MML integrated circuit device, when there are a large number of input and output data buses for the memory block, a large number of data buses may need to be added between the memory block and the buffer memory for normal operation and between the BIST circuit and the memory block for self-test. Moreover, a large number of data buses may need to be added between the multiplexer and the memory block in order to directly access the memory block from outside the MML integrated circuit device. The addition of these buses may unduly increase the size of the MML integrated circuit device. Moreover, it may be difficult to test the performance of the memory block during its normal operation when it is communicating only with the buffer memory.